HD6417618A datasheet(537/646 Pages) RENESAS

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Section 19 User Debugging Interface (H-UDI)

Rev. 6.00 Jun. 12, 2007 Page 505 of 610

REJ09B0131-0600

19.4.2

Reset Configuration

Table 19.4

Reset Configuration

ASEMD*1

RES

TRST

LSI State

High

Low

Normal reset and H-UDI reset

High

Normal reset

High

Low

H-UDI reset only

High

Normal operation

Low

Reset hold*

High

Normal reset

High

Low

H-UDI reset only

High

Normal operation

Notes: 1. Selects to normal mode or ASE mode.

ASEMD0 = high: normal mode

ASEMD0 = low: ASE mode

2. In ASE mode, the reset hold state is entered by driving the

RES and TRST pins low for

the given time. In this state, the CPU does not start up, even if the

RES pin is driven

high. After that, when the

TRST pin is driven high, H-UDI operation is enabled, but the

CPU does not start up. The reset hold state is canceled by the following: another

RES

assert (power-on reset) or

TRST reassert.

19.4.3

TDO Output Timing

The timing of data output from the TDO differs according to the command type set in SDIR. The

timing changes at the TCK falling edge when JTAG commands (EXTEST, CLAMP, HIGHZ,

SAMPLE/PRELOAD, IDCODE, and BYPASS) are set. This is a timing of the JTAG standard.

When the H-UDI commands (H-UDI reset negate, H-UDI reset assert, and H-UDI interrupt) are

set, the TDO signal is output at the TCK rising edge earlier than the JTAG standard by a half

cycle.

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