HD6417618A datasheet(137/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 105 of 610

REJ09B0131-0600

Section 7 Bus State Controller (BSC)

The bus state controller (BSC) outputs control signals for various types of memory that is

connected to the external address space and external devices. The BSC functions enable this LSI

to connect directly with SRAM, SDRAM, and other memory storage devices, and external

devices.

7.1

Features

The BSC has the following features.

• External address space

 A maximum 32 or 64 Mbytes for each of the areas, CS0, CS3, CS4, CS5B, and CS6B,

totally 256 Mbytes (divided into five areas)

 A maximum 64 Mbytes for each of the six areas, CS0, CS3, CS4, CS5, and CS6, totally

320 Mbytes (divided into five areas)

 Can specify the normal space interface, byte-selection SRAM, SDRAM, PCMCIA for each

address space

 Can select the data bus width (8 or 16 bits) for each address space

 Can control the insertion of wait cycles for each address space

 Can control the insertion of wait cycles for each read access and write access

 Can control the insertion of idle cycles in the consecutive access for five cases

independently: read-write (in same space/different space), read-read (in same

space/different space), or the first cycle is a write access

• Normal space interface

 Supports the interface that can directly connect to the SRAM

• SDRAM interface

 Can connect directly to SDRAM in area 3

 Multiplex output for row address/column address

 Efficient access by single read/single write

 High-speed access by bank-active mode

 Supports auto-refreshing and self-refreshing

• Byte-selection SRAM interface

 Can connect directly to byte-selection SRAM

HD6417618A 数据表(PDF) 137 Page - Renesas Technology Corp