HD6417618A datasheet(139/646 Pages) RENESAS

部件名	HD6417618A

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 107 of 610

REJ09B0131-0600

The block diagram of the BSC is shown in figure 7.1.

CMNCR

CS0WCR

CS6BWCR

CS0BCR

CS6BBCR

SDCR

RTCSR

RTCNT

RTCOR

Comparator

Bus

mastership

controller

Wait

controller

Area

controller

Internal master

module

Internal slave

module

Memory

controller

Refresh

controller

BSC

CS0, CS3, CS4,

CS5B (CE1A),

CS6B (CE1B)

WAIT

MD5

IOIS16

A25 to A0, D15 to D0,

BS, RD/WR, RD,

WE1 (BE1, DQMLU, WE),

WE0 (BE0, DQMLL),

ICIOWR, ICIORD,

RAS, CAS,

CKE,

CE2A, CE2B

[Legend]

CMNCR:

Common control register

CSnWCR: CSn space wait control register (n = 0, 3, 4, 5B, 6B)

RWTCNT: Reset wait counter

CSnBCR:

CSn space bus control register (n = 0, 3, 4, 5B, 6B)

SDCR:

SDRAM control register

RTCSR:

Refresh timer control/status register

RTCNT:

Refresh timer counter

RTCOR:

Refresh time constant register

RWTCNT

Figure 7.1 Block Diagram of BSC

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