HD6417618A datasheet(207/646 Pages) RENESAS

部件名	HD6417618A

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

标志

207 / 646 page

Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 175 of 610

REJ09B0131-0600

Figure 7.23 shows the auto-refreshing cycle timing. After starting the auto-refreshing, PALL

command is issued in the Tp cycle to make all the banks to precharged state from active state

when some bank is being precharged. Then the REF command is issued in the Trr cycle after

inserting idle cycles of which number is specified by bits WTRP1 and WTRP0 in CSnWCR. A

new command is not issued for the duration of the number of cycles specified by bits WTRC1

and WTRC0 in CSnWCR after the Trr cycle. Bits WTRC1 and WTRC0 in CSnWCR must be

set so as to satisfy the SDRAM refreshing cycle time (tRC). A Tpw cycle is inserted between

the Tp cycle and Trr cycle when the setting of bits WTRP1 and WTRP0 in CSnWCR is longer

than or equal to one cycle.

A25 to A0

CSn

RD/

Tpw

Trr

Trc

Hi-z

RAS

DQMxx

CAS

CKIO

D15 to D0

A11*

Note: * Address pin to be connected to pin A10 of SDRAM.

Figure 7.23 Auto-Refreshing Timing

HD6417618A 数据表(PDF) 207 Page - Renesas Technology Corp