HD6417618A datasheet(211/646 Pages) RENESAS

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Section 7 Bus State Controller (BSC)

Rev. 6.00 Jun. 12, 2007 Page 179 of 610

REJ09B0131-0600

CKIO

A25 to A0

CSn

RD/

RAS

DQMxx

D15 to D0

Tpw

Trr

A11*

CAS

Note: * Address pin to be connected to pin A10 of SDRAM.

Trc

Tmw

Hi-Z

Tnop

Trc

Trr

Trc

REF

MRS

PALL

Figure 7.25 Write Timing for SDRAM Mode Register (Based on JEDEC)

7.5.6

Byte-Selection SRAM Interface

The byte-selection SRAM interface is for access to SRAM which has a byte-selection pin (

WEn

(

BEn)). This interface is used to access to SRAM which has 16-bit data pins and upper and lower

byte selection pins, such as UB and LB.

When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the

byte-selection SRAM interface is the same as that for the normal space interface. While in read

access of a byte-selection SRAM interface, the byte-selection signal is output from the

WEn

(

BEn) pin, which is different from that for the normal space interface. The basic access timing is

shown in figure 7.26. In write access, data is written to the memory according to the timing of the

byte-selection pin (

WEn (BEn)). For details, refer to the data sheet for the corresponding memory.

If the BAS bit in CSnWCR is set to 1, the

WEn (BEn) pin and RD/WR pin timings change. The

basic access timing is shown in figure 7.27. In write access, data is written to the memory

according to the timing of the write enable pin (RD/

WR). The data hold timing from RD/WR

negation to data write must be secured by setting bits HW1 to HW0 in CSnWCR. Figure 7.28

shows the access timing when a software wait is specified.

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