R5F3650MDFB datasheet(8/829 Pages) RENESAS

8 / 829 page

A - 1

SFR Page Reference

B-1

Overview .................................................................................................. 1

1.1

Features .............................................................................................................. 1

1.1.1

Applications .................................................................................................. 1

1.2

Specifications ...................................................................................................... 2

1.3

Product List ........................................................................................................ 8

1.4

Block Diagram ................................................................................................... 10

1.5

Pin Assignments................................................................................................ 13

1.6

Pin Functions..................................................................................................... 24

Central Processing Unit (CPU)............................................................... 32

2.1

Data Registers (R0, R1, R2, and R3)................................................................ 32

2.2

Address Registers (A0 and A1)......................................................................... 33

2.3

Frame Base Register (FB) ................................................................................ 33

2.4

Interrupt Table Register (INTB) ......................................................................... 33

2.5

Program Counter (PC) ...................................................................................... 33

2.6

User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ............................. 33

2.7

Static Base Register (SB).................................................................................. 33

2.8

Flag Register (FLG)........................................................................................... 33

2.8.1

Carry Flag (C Flag)..................................................................................... 33

2.8.2

Debug Flag (D Flag) ................................................................................... 33

2.8.3

Zero Flag (Z Flag)....................................................................................... 33

2.8.4

Sign Flag (S Flag)....................................................................................... 33

2.8.5

2.8.6

Overflow Flag (O Flag) ............................................................................... 33

2.8.7

Interrupt Enable Flag (I Flag)...................................................................... 33

2.8.8

Stack Pointer Select Flag (U Flag) ............................................................. 34

2.8.9

Processor Interrupt Priority Level (IPL) ...................................................... 34

2.8.10

Reserved Space ......................................................................................... 34

Address Space ....................................................................................... 35

3.1

Address Space .................................................................................................. 35

3.2

Memory Map ..................................................................................................... 36

3.3

Accessible Area in Each Mode.......................................................................... 37

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