R5F3650MDFB datasheet(12/829 Pages) RENESAS

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9.6

Notes on Power Control .................................................................................. 150

9.6.1

CPU Clock ................................................................................................ 150

9.6.2

Wait Mode ................................................................................................ 150

9.6.3

Stop Mode ................................................................................................ 151

9.6.4

Low Current Consumption Read Mode .................................................... 151

10. Processor Mode ................................................................................... 152

10.1

Introduction...................................................................................................... 152

10.2

Registers ......................................................................................................... 153

10.2.1

Processor Mode Register 0 (PM0) ........................................................... 153

10.2.2

Processor Mode Register 1 (PM1) ........................................................... 154

10.2.3

Program 2 Area Control Register (PRG2C) ............................................. 156

10.3

Operations....................................................................................................... 157

10.3.1

Processor Mode Settings ......................................................................... 157

11. Bus ....................................................................................................... 159

11.1

Introduction...................................................................................................... 159

11.2

Registers ......................................................................................................... 160

11.2.1

Chip Select Control Register (CSR) ......................................................... 161

11.2.2

Chip Select Expansion Control Register (CSE)........................................ 162

11.2.3

External Area Wait Control Expansion Register (EWC) ........................... 163

11.2.4

External Area Recovery Cycle Control Register (EWR)........................... 164

11.3

Operations....................................................................................................... 165

11.3.1

Common Specifications of Internal Bus and External Bus ....................... 165

11.3.2

Internal Bus .............................................................................................. 166

11.3.3

External Bus ............................................................................................. 167

11.3.4

External Bus Mode ................................................................................... 167

11.3.5

External Bus Control................................................................................. 168

11.4

Notes on Bus................................................................................................... 181

11.4.1

Reading Data Flash.................................................................................. 181

11.4.2

External Bus ............................................................................................. 181

11.4.3

External Access Soon After Writing to the SFRs...................................... 181

12. Memory Space Expansion Function ..................................................... 182

12.1

Introduction...................................................................................................... 182

12.2

Registers ......................................................................................................... 182

R5F3650MDFB 数据表(PDF) 12 Page - Renesas Technology Corp

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