数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

H8SX/1663 数据表(PDF) 815 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 815 Page - Renesas Technology Corp

Back Button H8SX/1663 Datasheet HTML 811Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 812Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 813Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 814Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 815Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 816Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 817Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 818Page - Renesas Technology Corp H8SX/1663 Datasheet HTML 819Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 815 / 1158 page
background image
Section 16 USB Function Module (USB)
Rev.1.00 Jun. 07, 2006 Page 763 of 1102
REJ09B0294-0100
16.3.8
Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 1
(ISR1).
Bit
Bit Name
Initial Value
R/W
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
EP3 TR
0
R/W
1
EP3 TS
0
R/W
0
VBUSF
0
R/W
Bit
Bit Name
Initial
Value
R/W
Description
7
6
5
4
3
0
0
0
0
0
R
R
R
R
R
Reserved
These bits are always read as 0. The write value
should always be 0.
2
EP3 TR
0
R/W
EP3 Transfer Request
1
EP3 TS
0
R/W
EP3 Transmission Complete
0
VBUSF
0
R/W
USB Bus Connect
16.3.9
Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set
to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the
CPU. The interrupt vector number is determined by the contents of interrupt select register 2
(ISR2).
Bit
Bit Name
Initial Value
R/W
7
SSRSME
0
R/W
6
0
R
5
0
R
4
SURSE
0
R/W
3
CFDN
0
R/W
2
0
R
1
SETCE
0
R/W
0
SETIE
0
R/W



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com