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H8SX/1663 数据表(PDF) 816 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 816 Page - Renesas Technology Corp

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Section 16 USB Function Module (USB)
Rev.1.00 Jun. 07, 2006 Page 764 of 1102
REJ09B0294-0100
Bit
Bit Name
Initial
Value
R/W
Description
7
SSRSME
0
R/W
Resume Detection for Software Standby Cancel
For the details of the operation, see section 16.5.3,
Suspend and Resume Operations.
6, 5
All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
4
SURSE
0
R/W
Suspend/Resume Detection
For the details of the operation, see section 16.5.3,
Suspend and Resume Operations.
3
CFDN
0
R/W
End Point Information Load End
2
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
SETCE
0
R/W
Set_Configuration Command Detection
0
SETIE
0
R/W
Set_Interface Command Detection
16.3.10
EP0i Data Register (EPDR0i)
EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in
the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means
of EP0iCLR in the FCLR register.
Bit
Bit Name
Initial Value
R/W
7
D7
Undefined
W
6
D6
Undefined
W
5
D5
Undefined
W
4
D4
Undefined
W
3
D3
Undefined
W
2
D2
Undefined
W
1
D1
Undefined
W
0
D0
Undefined
W
Bit
Bit Name
Initial
Value
R/W
Description
7 to 0
D7 to D0
Undefined W
Data register for control-in transfer



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