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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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H8SX/1663 数据表(PDF) 820 Page - Renesas Technology Corp |
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H8SX/1663 数据表(HTML) 820 Page - Renesas Technology Corp |
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820 / 1158 page  Section 16 USB Function Module (USB) Rev.1.00 Jun. 07, 2006 Page 768 of 1102 REJ09B0294-0100 16.3.17 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU). Bit Bit Name Initial Value R/W 7 — 0 R 6 — 0 R 5 — 0 R 4 — 0 R 3 — 0 R 2 — 0 R 1 — 0 R 0 — 0 R Bit Bit Name Initial Value R/W Description 7 to 0 — All 0 R Number of received bytes for endpoint 1 16.3.18 Trigger Register (TRG) TRG generates one-shot triggers to control the transfer sequence for each endpoint. Bit Bit Name Initial Value R/W 7 Undefined 6 EP3 PKTE Undefined W 5 EP1 RDFN Undefined W 4 EP2 PKTE Undefined W 3 Undefined 2 EP0s RDFN Undefined W 1 EP0o RDFN Undefined W 0 EP0i PKTE Undefined W Bit Bit Name Initial Value R/W Description 7 Undefined Reserved The write value should always be 0. 6 EP3 PKTE Undefined W EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit. |
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