H8SXSLASH1663 datasheet(823/1158 Pages) RENESAS

823 / 1158 page

Section 16 USB Function Module (USB)

Rev.1.00 Jun. 07, 2006 Page 771 of 1102

REJ09B0294-0100

16.3.20

FIFO Clear Register (FCLR)

FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the

data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared.

Do not clear a FIFO buffer during transfer.

Bit

Bit Name

Initial Value

R/W



Undefined



EP3 CLR

Undefined

EP1 CLR

Undefined

EP2 CLR

Undefined



Undefined



Undefined



EP0o CLR

Undefined

EP0i CLR

Undefined

Bit

Bit Name

Initial

Value

R/W

Description



Undefined



Reserved

The write value should always be 0.

EP3 CLR

Undefined

EP3 Clear

Writing 1 to this bit initializes the endpoint 3 transmit

FIFO buffer.

EP1 CLR

Undefined

EP1 Clear

Writing 1 to this bit initializes both sides of the

endpoint 1 receive FIFO buffer.

EP2 CLR

Undefined

EP2 Clear

Writing 1 to this bit initializes both sides of the

endpoint 2 transmit FIFO buffer.



Undefined



Reserved

The write value should always be 0.

EP0o CLR

Undefined

EP0o Clear

Writing 1 to this bit initializes the endpoint 0 receive

FIFO buffer.

EP0i CLR

Undefined

EP0i Clear

Writing 1 to this bit initializes the endpoint 0 transmit

FIFO buffer.

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