H8SXSLASH1663 datasheet(894/1158 Pages) RENESAS

894 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 842 of 1102

REJ09B0294-0100

ICDRS

ICDRR

RDRF

SDA

(Master output)

SCL

(Slave output)

SDA

(Slave output)

SCL

(Master output)

Data 2

Data 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

User

processing

[3] Set ACKBT

[3] Read ICDRR

[4] Read ICDRR

Figure 17.12 Slave Receive Mode Operation Timing 2

17.4.6

Noise Canceler

The logic levels at the SCL and SDA pins are routed through the noise cancelers before being

latched internally. Figure 17.13 shows a block diagram of the noise canceler circuit.

The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL

(or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the

outputs of both latches agree. If they do not agree, the previous value is held.

Sampling clock

Sampling

clock

SCL input

SDA input

Latch

System clock period

Latch

Compare

match

detection

circuit

Internal SCL

internal SDA

Sampling clock

Figure 17.13 Block Diagram of Noise Canceler

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