H8SXSLASH1663 datasheet(896/1158 Pages) RENESAS

896 / 1158 page

Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 844 of 1102

REJ09B0294-0100

Yes

RDRF = 1?

Yes

RDRF = 1?

Yes

STOP = 1?

Yes

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

Master receive mode

[1]

Clear TEND, set to master receive mode, then clear TDRE*1*2

[2]

Set acknowledge to the transmitting device*1*2

[3]

Dummy read ICDRR*1*2

[4]

Wait for 1 byte of data to be received*2

[5]

Check if (last receive -1)*2

[6]

Read the receive data*2

[7]

Set acknowledge of the last byte. Disable continuous reception

(RCVD = 1).*2

[8]

Read receive data of (last byte -1).*2

[9]

Wait for the last byte to be received

[10] Clear the STOP flag

[11] Issue the stop condition

[12] Wait for the creation of stop condition

[13] Read the receive data of the last byte

[14] Clear RCVD to 0

[15] Set to slave receive mode

Clear TEND in ICSR

Set TRS = 0 (ICCRA)

Clear TDRE in ICSR

Set ACKBT = 0 (ICIER)

Dummy read ICDRR

Dummy read ICSR

Last

receive -1?

Read ICDRR

Set ACKBT = 1 (ICIER)

Set RCVD = 1 (ICCRA)

Read ICDRR

Read RDRF in ICSR

Clear STOP in ICSR

Write BBSY = 0 and

SCP = 0

Read STOP in ICSR

Read ICDRR

Set RCVD = 0 (ICCRA)

Set MST = 0 (ICCRA)

End

Note: 1.

Do not generate an interrupt during steps [1] to [3].

For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7].

In step [8], read ICDRR (dummy read).

Figure 17.15 Sample Flowchart for Master Receive Mode

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