H8SXSLASH1663 datasheet(895/1158 Pages) RENESAS

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Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 843 of 1102

REJ09B0294-0100

17.4.7

Example of Use

Sample flowcharts in respective modes that use the I

2C bus interface are shown in figures 17.14 to

17.17.

Yes

[1]

[2]

[3]

[4]

[5]

[6]

[7]

[8]

[9]

[10]

[11]

[12]

[13]

[14]

[15]

Start

[1]

Detect the state of the SCL and SDA lines

[2]

Set to master transmit mode

[3]

Issue the start condition

[4]

Set the transmit data for the first byte (slave address + R/W)

[5]

Wait for 1 byte of data to be transmitted

[6]

Detect the acknowledge bit, transferred from the specified slave device

[7]

Set the transmit data for the second and subsequent data (except for the

last byte)

[8]

Wait for ICDRT empty

[9]

Set the last byte of transmit data

[10] Wait for the completion of transmission of the last byte

[11] Clear the TEND flag

[12] Clear the STOP flag

[13] Issue the stop condition

[14] Wait for the creation of the stop condition

[15] Set to slave receive mode. Clear TDRE.

Initial settings

Read BBSY in ICCRB

Set MST = 1 and

TRS = 1 in ICCRA

BBSY = 0?

Write BBSY = 1

and SCP = 0

Write the transmit

data in ICDRT

Read TEND in ISCR

TEND = 1?

Read ACKBR in ICIER

ACKBR = 0?

Transmit

mode?

Read TDRE in ICSR

TDRE = 1?

Last byte?

Write the transmit data to ICDRT

Read TEND in ICSR

TEND = 1?

Clear TEND in ICSR

Clear STOP in ICSR

Write BBSY = 0

and SCP = 0

Read STOP in ICSR

STOP = 1?

Set MST = 0

and TRS = 0 in ICCRA

Clear TRDE in ICSR

End

Master receive mode

Write the transmit data to ICDRT

Figure 17.14 Sample Flowchart of Master Transmit Mode

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