H8SXSLASH1663 datasheet(899/1158 Pages) RENESAS

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Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 847 of 1102

REJ09B0294-0100

17.5

Interrupt Request

There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,

NACK detection, STOP recognition, and arbitration lost. Table 17.3 shows the contents of each

interrupt request.

Table 17.3

Interrupt Requests

Interrupt Request

Abbreviation

Interrupt Condition

Transmit Data Empty

TXI

(TDRE = 1)

⋅ (TIE = 1)

Transmit End

TEI

(TEND = 1)

⋅ (TEIE = 1)

Receive Data Full

RXI

(RDRF = 1)

⋅ (RIE = 1)

Stop Recognition

STPI

(STOP = 1)

⋅ (STIE = 1)

NACK Detection

MAKI

{(NACKF = 1)

+ (AL = 1)} ⋅ (NAKIE = 1)

Arbitration Lost

17.6

Bit Synchronous Circuit

This module has a possibility that the high-level period is shortened in the two states described

below.

In master mode,

• When SCL is driven low by the slave device

• When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or

pull-up resistance)

Therefore, this module monitors SCL and communicates bit by bit in synchronization.

Figure 17.18 shows the timing of the bit synchronous circuit, and table 17.4 shows the time when

SCL output changes from low to Hi-Z and the period which SCL is monitored.

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