H8SXSLASH1663 datasheet(900/1158 Pages) RENESAS

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Section 17 I

2C Bus Interface 2 (IIC2)

Rev.1.00 Jun. 07, 2006 Page 848 of 1102

REJ09B0294-0100

SCL monitor timing

reference clock

Internal SCL

SCL

Figure 17.18 Timing of the Bit Synchronous Circuit

Table 17.4

Time for Monitoring SCL

CKS3

CKS2

Time for Monitoring SCL

7.5 tcyc

19.5 tcyc

17.5 tcyc

41.5 tcyc

17.7

Usage Notes

1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition.

The ninth falling edge can be confirmed by monitoring the SCLO bit in the I

2C bus control

If a stop or a repeated start condition is issued at certain timing in either of the following cases,

the stop or repeated start condition may be issued incorrectly.

 The rising time of the SCL signal exceeds the time given in section 17.6, Bit Synchronous

Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance).

 The bit synchronous circuit is activated because a slave device holds the SCL bus low

during the eighth clock.

2. The WAIT bit in the I

2C bus mode register (ICMR) must be held 0.

If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one

transfer clock cycle during the eighth clock, the high level period of the ninth clock may be

shorter than a given period.

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