H8SXSLASH1663 datasheet(905/1158 Pages) RENESAS

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Section 18 A/D Converter

Rev.1.00 Jun. 07, 2006 Page 853 of 1102

REJ09B0294-0100

18.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.

ADF

R/(W)*

ADIE

R/W

ADST

R/W



CH3

R/W

CH2

R/W

CH1

R/W

CH0

R/W

Bit

Bit Name

Initial Value

R/W

Note: * Only 0 can be written to this bit, to clear the flag.

Bit

Bit Name

Initial

Value

R/W

Description

ADF

R/(W)* A/D End Flag

A status flag that indicates the end of A/D conversion.

[Setting conditions]

• When A/D conversion ends in single mode

• When A/D conversion ends on all specified channels

in scan mode

[Clearing conditions]

• When 0 is written after reading ADF = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

• When the DMAC or DTC is activated by an ADI

interrupt and ADDR is read

ADIE

R/W

A/D Interrupt Enable

When this bit is set to 1, ADI interrupts by ADF are

enabled.

ADST

R/W

A/D Start

Clearing this bit to 0 stops A/D conversion, and the A/D

converter enters wait state.

Setting this bit to 1 starts A/D conversion. In single mode,

this bit is cleared to 0 automatically when A/D conversion

on the specified channel ends. In scan mode, A/D

conversion continues sequentially on the specified

channels until this bit is cleared to 0 by software, a reset,

or hardware standby mode.

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