H8SXSLASH1663 datasheet(908/1158 Pages) RENESAS

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Section 18 A/D Converter

Rev.1.00 Jun. 07, 2006 Page 856 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

1, 0



All 0

Reserved

These are read-only bits and cannot be modified.

[Legend]

X: Don't care

Note:

To set A/D conversion to start by the

ADTRG pin, the DDR bit and ICR bit for the

corresponding pin should be set to 0 and 1, respectively. For details, refer to section 9,

I/O Ports.

18.4

Operation

The A/D converter operates by successive approximation with 10-bit resolution. It has two

operating modes: single mode and scan mode. When changing the operating mode or analog input

channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0 to halt A/D

conversion. The ADST bit can be set to 1 at the same time as the operating mode or analog input

channel is changed.

18.4.1

Single Mode

In single mode, A/D conversion is to be performed only once on the analog input of the specified

single channel.

1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by

software or an external trigger input.

2. When A/D conversion is completed, the A/D conversion result is transferred to the

corresponding A/D data register of the channel.

3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set

to 1 at this time, an ADI interrupt request is generated.

4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when

A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0

during A/D conversion, A/D conversion stops and the A/D converter enters wait state.

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