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H8SX/1663 数据表(PDF) 909 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 909 Page - Renesas Technology Corp

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Section 18 A/D Converter
Rev.1.00 Jun. 07, 2006 Page 857 of 1102
REJ09B0294-0100
ADIE
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
Set*
Set*
Set*
A/D conversion start
Clear*
Clear*
Waiting for conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
Waiting for conversion
Reading A/D conversion result
Reading A/D conversion result
A/D conversion 1
A/D conversion 2
A/D conversion result 1
A/D conversion result 2
Waiting for
conversion
Note: *
↓ indicates the timing of instruction execution by software.
Figure 18.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
18.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified
channels up to four or eight channels.
1. When the ADST bit in ADCSR is set to 1 by software, TPU, TMR, or an external trigger
input, A/D conversion starts on the first channel in the group. Consecutive A/D conversion on
a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight
channels (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is
performed on four channels, A/D conversion starts on AN4 when CH3 and CH2 = B'01. When
consecutive A/D conversion is performed on eight channels, A/D conversion starts on AN0
when CH3 = B'0.
2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially
transferred to the corresponding ADDR of each channel.



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