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H8SX/1663 数据表(PDF) 910 Page - Renesas Technology Corp

部件名 H8SX/1663
功能描述  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1158 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

H8SX/1663 数据表(HTML) 910 Page - Renesas Technology Corp

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Section 18 A/D Converter
Rev.1.00 Jun. 07, 2006 Page 858 of 1102
REJ09B0294-0100
3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of
the first channel in the group starts again.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
ADST
ADF
ADDRA
ADDRB
ADDRC
ADDRD
Set*1
Clear*1
Clear*1
*2
Waiting for conversion
Channel 0 (AN0)
operation state
Channel 1 (AN1)
operation state
Channel 2 (AN2)
operation state
Channel 3 (AN3)
operation state
Waiting for
conversion
A/D
conver-
sion 1
A/D conversion result 3
Waiting for conversion
Waiting for
conversion
Waiting for conversion
A/D conversion result 2
A/D conversion result 4
A/D
conver-
sion 5
A/D
conver-
sion 4
A/D conversion time
Waiting for conversion
A/D
conver-
sion 3
Waiting for conversion
Waiting for conversion
Waiting for conversion
A/D
conver-
sion 2
A/D conversion result 1
Transfer
A/D conversion consecutive execution
Notes: 1.
2.
↓ indicates the timing of instruction execution by software.
Data being converted is ignored.
Figure 18.3 Example of A/D Conversion
(Scan Mode, Three Channels (AN0 to AN2) Selected)



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