H8SXSLASH1663 datasheet(966/1158 Pages) RENESAS

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Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 914 of 1102

REJ09B0294-0100

The procedure program must be executed in an area other than the flash memory to be

programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-

chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM,

user MAT, and external space) is shown in section 21.7.4, On-Chip Program and Storable Area for

Program Data. The following description assumes that the area to be programmed on the user

MAT is erased and that program data is prepared in the consecutive area.

The program data for one programming operation is always 128 bytes. When the program data

exceeds 128 bytes, the start address of the programming destination and program data parameters

are updated in 128-byte units and programming is repeated. When the program data is less than

128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is

H'FF, the program processing time can be shortened.

1. Select the on-chip program to be downloaded and the download destination. When the PPVS

bit in FPCS is set to 1, the programming program is selected. Several programming/erasing

programs cannot be selected at one time. If several programs are selected, a download error is

returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download

destination is specified by FTDAR.

2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1

to request download of the on-chip program.

3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the

SCO bit to 1, all of the following conditions must be satisfied.

 RAM emulation mode has been canceled.

 H'A5 is written to FKEY.

 Setting the SCO bit is executed in the on-chip RAM.

When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared

to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the

procedure program. The download result can be confirmed by the return value of the DPFR

parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the

on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a

value other than the return value (e.g. H'FF). Since particular processing that is accompanied

by bank switching as described below is performed when download is executed, initialize the

VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately

after the SCO bit is set to 1.

 The user-MAT space is switched to the on-chip program storage area.

 After the program to be downloaded and the on-chip RAM start address specified by

FTDAR are checked, they are transferred to the on-chip RAM.

 FPCS, FECS, and the SCO bit in FCCS are cleared to 0.

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