H8SXSLASH1663 datasheet(967/1158 Pages) RENESAS

967 / 1158 page

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 915 of 1102

REJ09B0294-0100

 The return value is set in the DPFR parameter.

 After the on-chip program storage area is returned to the user-MAT space, the procedure

program is resumed. After that, VBR can be set again.

 The values of general registers of the CPU are held.

 During download, no interrupts can be accepted. However, since the interrupt requests are

held, when the procedure program is resumed, the interrupts are requested.

 To hold a level-detection interrupt request, the interrupt must continue to be input until the

download is completed.

 Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the

SCO bit to 1.

 If access to the flash memory is requested by the DMAC or DTC during download, the

operation cannot be guaranteed. Make sure that an access request by the DMAC or DTC is

not generated.

4. FKEY is cleared to H'00 for protection.

5. The download result must be confirmed by the value of the DPFR parameter. Check the value

of the DPFR parameter (one byte of start address of the download destination specified by

FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally.

If the value is not H'00, the source that caused download to fail can be investigated by the

description below.

 If the value of the DPFR parameter is the same as that before downloading, the setting of

the start address of the download destination in FTDAR may be abnormal. In this case,

confirm the setting of the TDER bit in FTDAR.

 If the value of the DPFR parameter is different from that before downloading, check the SS

bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY

setting, respectively.

6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The

settable operating frequency of the FPEFEQ parameter ranges from 8 to 50 MHz. When the

frequency is set otherwise, an error is returned to the FPFR parameter of the initialization

program and initialization is not performed. For details on setting the frequency, see section

21.6.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of

CPU).

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