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M32C/86T 数据表(PDF) 83 Page - Renesas Technology Corp |
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M32C/86T 数据表(HTML) 83 Page - Renesas Technology Corp |
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83 / 505 page ![]() Page 60 9 7 4 f o 5 0 0 2 , 8 0 . p e S 0 0 . 1 . v e R 0 0 1 0 - 4 0 2 0 B 9 0 J E R 8. Bus ) T 6 8 / C 2 3 M , 6 8 / C 2 3 M ( p u o r G 6 8 / C 2 3 M 8.2.4 Bus Timing Bus cycle for the internal ROM and internal RAM is basically one BCLK cycle. When the PM12 bit in the PM1 register is set to "1" (wait state), the bus cycles are two BCLK cycles. Bus cycles for the SFR are basically two BCLK cycles. When the PM13 bit in the PM1 register is set to "1" (2 wait states), the bus cycles are three BCLK cycles. Basic bus cycle for an external space is 2ø (1ø+1ø) to read and to write. Bus cycle is selected by the EWCRi register (i=0 to 3) from 12 types of separate bus settings and 7 types of multiplexed bus settings. If the EWCRi04 to EWCRi00 bits are set to "000112" (1ø+3ø), bus cycles are four BCLK cycles. Figure 8.3 shows the EWCRi register. Figures 8.4 to 8.8 show bus timing in an external space. Figure 8.3 EWCR0 to EWCR3 Registers Symbol Address After Reset EWCR0 to EWCR3 004816, 004916, 004A16, 004B16 X0X0 00112 External Space Wait Control Register i (i=0 to 3)(3) RW RW RW RW RW RW RW EWCRi00 EWCRi01 EWCRi03 EWCRi04 (b5) (b7) EWCRi06 EWCRi02 0 0 0 0 1: 1 φ + 1φ 0 0 0 1 0: 1 φ + 2φ 0 0 0 1 1: 1 φ + 3φ 0 0 1 0 0: 1 φ + 4φ 0 0 1 0 1: 1 φ + 5φ 0 0 1 1 0: 1 φ + 6φ 0 1 0 1 0: 2 φ + 2φ 0 1 0 1 1: 2 φ + 3φ 0 1 1 0 0: 2 φ + 4φ 0 1 1 0 1: 2 φ + 5φ 1 0 0 1 1: 3 φ + 3φ 1 0 1 0 0: 3 φ + 4φ 1 0 1 0 1: 3 φ + 5φ 1 0 1 1 0: 3 φ + 6φ Do not set values other than the above Bit Name Function Bit Symbol Bus Cycle Select Bit Nothing is assigned. When read, its content is indeterminate. Nothing is assigned. When read, its content is indeterminate. Recovery Cycle Addition Select Bit 0 : Adds no recovery cycle when accessing external space i 1 : Adds a recovery cycle when accessing external space i b7 b6 b5 b4 b3 b2 b1 b0 b4 b3 b2 b1 b0 (1) (2) NOTES: 1. The number of bus cycles from "when bus access begins" to "when RD or WR signal becomes "L". 2. The number of bus cycles from "when RD or WR signal becomes "L" to "when it becomes "H". 3. The EWCR0 to EWCR3 registers in M32C/86T cannot be used. |
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