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M32C/86T 数据表(PDF) 91 Page - Renesas Technology Corp

部件名 M32C/86T
功能描述  RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES
PDF  505 Pages
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制造商  RENESAS [Renesas Technology Corp]
网页  http://www.renesas.com
标志 RENESAS - Renesas Technology Corp

M32C/86T 数据表(HTML) 91 Page - Renesas Technology Corp

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8.2.5 ALE Signal
The ALE signal latches an address of the multiplexed bus. Latch an address on the falling edge of the
ALE signal. The PM15 and PM14 bits in the PM1 register determine the output pin for the ALE signal.
The ALE signal is output to internal space and external space.
Figure 8.10 ALE Signal and Address/Data Bus
_______
8.2.6 RDY Signal
_______
The RDY signal facilitates access to external devices requiring longer access time. When a low-level ("L")
________
signal is applied to the RDY pin on the falling edge of the last BCLK of the bus cycle, wait states are
________
inserted into the bus cycle. When a high-level ("H") signal is applied to the RDY pin on the falling edge of
BCLK, the bus cycle starts running again.
________
Table 8.6 lists microcomputer states when the RDY signal inserts wait states into the bus cycle. Figure
_____
________
8.11 shows an example of the RD signal that is extended by the RDY signal.
Table 8.6 Microcomputer States in Wait State(1)
(1) 8-Bit Data Bus
(2) 16-Bit Data Bus
ALE
Address
Data
Address
D0/A0 to D7/A7
A8 to A15
ALE
Address
Data
Address
D0/A0 to D15/A15
A16 to A19
NOTES:
1. D0/A0 to D7/A7 are placed in high-impedance states when read.
2. When the multiplexed bus is selected for all CS areas, the address bus becomes an I/O port.
Address
Address or CS
Address or CS
A16 to A19
(1)
(1)
(2)
(2)
A20/CS3
A21/CS2
A22/CS1
A23/CS0
A20/CS3
A21/CS2
A22/CS1
A23/CS0
NOTES:
________
1. The RDY signal cannot be accepted immediately before software wait states are inserted.
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