ADATE304BBCZ datasheet(33/52 Pages) AD

部件名	ADATE304BBCZ

功能描述	200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH

PDF	52 Pages

Scroll/Zoom	100%

制造商	AD [Analog Devices]

网页	http://www.analog.com

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33 / 52 page

ADATE304

Rev. 0 | Page 33 of 52

SPI DETAILS

SCLK

SDIN

tCH

tCL

tCSSA

tCSHA

tCSHD

tCSSD

tDH

tDS

tCSW

SDOUT

DO_2LAST

DO_12LAST

DO_13LAST

DO_14LAST

DO_15LAST

DO_1LAST

DO_0LAST

tDO

DATA[14]

DATA[15]

CH[1]

R/W

ADDR[1]

ADDR[0]

Figure 63. SPI Timing Diagram

Table 17. Serial Peripheral Interface Timing Requirements

Symbol

Parameter

Min

Max

Unit

tCH

SCLK minimum high

9.0

tCL

SCLK minimum low

9.0

tCSHA

CS assert hold

3.0

tCSSA

CS assert setup

3.0

tCSHD

CS deassert hold

3.0

tCSSD

CS deassert setup

3.0

tDH

SDIN hold

3.0

tDS

SDIN setup

3.0

tDO

SDOUT data out

15.0

tCSW

CS minimum between assertions1

SCLK cycles

CS minimum directly after a read request

SCLK cycles

tCSTP

Minimum delay after CS is deasserted before SCLK can be

stopped (not shown in

); this allows any internal

operations to complete

Figure 63

SCLK cycles

1 An extra cycle is needed after a read request to prime the read data into the SPI shift register.

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