struction; and bit 0 is not used. To shift control data

into COMBO IIG, CCLK must be pulsed high 8

times while CS is low. Data on the CI or CI/O input

is shifted into the serial input register on the falling

edge of each CCLK pulse. After all data is shifted

in, the content s of the input shift register are de-

coded, and may indicate that a 2nd byte of control

data will follow. This second byte may either be de-

fined by a secondbyte-wide CS pulse or may follow

the first continuously,i.e. it is not mandatory for CS

to return high in between the first and second con-

trol bytes. On the falling edge of the 8

pulse in the 2nd control byte the data is loaded into

the appropriateprogrammable register. CS may re-

main low continuously when programming succes-

sive registers, if desired.However CS shouldbe set

high when no data transfers are in progress.

To readbackinterface Latch data or status informa-

tion from COMBO IIG, the first byte of the appropri-

ate instruction is strobed in during the first CS pulse,

as defined in table 1. CS must then be taken low for

a further 8 CCLK cycles, during which the data is

shifted onto the CO or CI/O pin on the rising edges

of CCLK. When CS is high the CO or CI/O pin is in

the high-impedanceTRI-STATE, enabling the CI/O

pins of many devices to be multiplexed together.

Thus, to summarize, 2-byte READ and WRITE in-

structions may use either two 8-bit wide CS pulses

or a single 16-bit wide CS pulse.

Function

Byte 1

Byte 2

7

6

5

43

21

0

Single Byte Power–up/down

PXXXXX

0

X

None

Write Control Register

Read–back Control Register

P

P

0

0

0

0

0

0

0

0

0

1

1

1

X

X

See Table 2

See Table 2

Write Latch Direction Register (LDR)

Read Latch Direction Register

P

P

0

0

0

0

1

1

0

0

0

1

1

1

X

X

See Table 4

See Table 4

Write Latch Content Register (ILR)

Read Latch Content Register

P

P

0

0

0

0

0

0

1

1

0

1

1

1

X

X

See Table 5

See Table 5

Write Transmit Time–slot/port

Read–back Transmit Time–slot/port

P

P

1

1

0

0

1

1

0

0

0

1

1

1

X

X

See Table 6

See Table 6

Write Receive Time–slot/port

Read–back Receive Time–slot/port

P

P

1

1

0

0

0

0

1

1

0

1

1

1

X

X

See Table 6

See Table 6

Write Transmit Gain Register

Read Transmit Gain Register

P

P

0

0

1

1

0

0

1

1

0

1

1

1

X

X

See Table 7

See Table 7

Write Receive Gain Register

Read Receive Gain Register

P

P

0

0

1

1

0

0

0

0

0

1

1

1

X

X

See Table 8

See Table 8

Write Hybrid Balance Register

≠ 1

Read Hybrid Balance Register

≠ 1

P

P

0

0

1

1

1

1

0

0

0

1

1

1

X

X

See Table 9

See Table 9

Write Hybrid Balance Register

≠ 2

Read Hybrid Balance Register

≠ 2

P

P

0

0

1

1

1

1

1

1

0

1

1

1

X

X

See Table 10

See Table 10

Write Hybrid Balance Register

≠ 3

Read Hybrid Balance Register

≠ 3

P

P

1

1

0

0

0

0

0

0

0

1

1

1

X

X

Table 1: Programmable Register Instructions

PROGRAMMABLE FUNCTIONS

POWER-UP/DOWN CONTROL

Following power-on initialization, power-up and

power-down control may be accomplished by

writing any of the control instructions listed in ta-

ble 1 into COMBO IIG with the ”P” bit set to ”0”

for power-up or ”1” for power-down. Normally it is

recommended that all programmable functions be

initially programmed while the device is powered

down. Power state control can then be included

with the last programming instruction or the sepa-

rate single-byte instruction. Any of the program-

mable registers may also be modified while the

device is powered-up or down be setting the ”P”

bit as indicated. When the power up or down con-

trol is entered as a single byte instruction, bit one

(1) must be set to a 0.

When a power-up command is given, all de-acti-

vated circuits are activated, but the TRI-STATE

after power-up.

Notes: 1. Bit 7 of bytes 1 and 2 is always the first bit clocked into or out of the CI, CO or CI/CO pin.

2. ”P” is the power-up/down control bit, see ”Power-up” section (”0” = Power Up ”1” = Power Down).

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