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TS5071 数据表(PDF) 2 Page - STMicroelectronics

部件名 TS5071
功能描述  PROGRAMMABLE CODEC/FILTER COMBO 2ND GENERATION
PDF  32 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

TS5071 数据表(HTML) 2 Page - STMicroelectronics

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TS5070 PIN FUNCTIONALITY (PLCC28)
No.
Name
Function
1
GND
Ground Input (+0V)
2VFR0
Analog Output
3VSS
Supply Input (-5V)
4
NC
Not Connected
5
NC
Not Connected
6
IL3
Digital Input or Output defined by LDR register content
7
IL2
Digital Input or Output defined by LDR register content
8FSR
Digital input
9DR1
Digital input sampled by BCLK falling edge
10
DR0
Digital input sampled by BCLK falling edge
11
CO
Digital output (shifted out on CCLK rising edge)
12
CI
Digital input (sampled on CCLK falling edge)
13
CCLK
Digital input (clock)
14
CS
Digital input (chip select for CI/CO)
15
MR
Digital Input
16
BCLK
Digital input (clock)
17
MCLK
Digital input
18
DX0
Digital output clocked by BCLK rising edge
19
DX1
Digital output clocked by BCLK rising edge
20
TSX0
Open drain output (pulled low by active DX0 time slot)
21
TSX1
Open drain output (pulled low by active DX1 time slot)
22
FSX
Digital input
23
IL5
Digital input or output defined by LDR register content
24
IL4
Digital input or output defined by LDR register content
25
IL1
Digital input or output defined by LDR register content
26
IL0
Digital input or output defined by LDR register content
27
VCC
Supply input (+5V)
28
VFXI
Analog input
HYBRID
BALANCE
FILTER
ENCODER
TX GAIN
TX
REGISTER
TX TIME SLOT
Vref
HYBAL 1
HYBAL 2
HYBAL 3
TIME-SLOT
ASSIGNMENT
CTL REG.
RX TIME SLOT
RX
REGISTER
RX GAIN
DECODER
AZ
TS5070/71
INTERFACE
LATCHES
LATCH DIR
LATCH CONT.
CONTROL
INTERFACE
DX0
DX1
TSX0
TSX1
FSX
BCLK
FSR
DR0
DR1
MCLK
MR
CS
CCLK
CO
CI
VSS=-5V
VCC=+5V
VFXI
VFRO
GND
IL5
IL4
IL3
IL2
IL1
IL0
D94TL135
TS5070 FUNCTIONAL DIAGRAM
TS5070 - TS5071
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