TS5070FN datasheet(19/32 Pages) STMICROELECTRONICS

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TIMING SPECIFICATIONS (continued)

PCM INTERFACE TIMING

Symbol

Parameter

Min.

Typ.

Max.

Unit

fBCLK

Frequency of BCLK (may vary from 64KHz to 4.096MHz in 8KHz

increments, TS5070 only)

4096

kHz

tWBH

Period of BCLK High (measured from VIH to VIH)

tWBL

Period of BCLK Low (measured from VIL to VIL)

tRB

Rise Time of BCLK (measured from VIL to VIH)30

tFB

Fall Time of BCLK (measured from VIH to VIL)30

tHBF

Hold Time, BCLK Low to FSX/R High or Low

tSFB

Setup Time FSX/R High to BCLK Low

tDBD

Delay Time, BCLK High to Data Valid (load = 100pF plus 2 LSTTL

loads)

tDBZ

Delay Time from BCLK8 Low to Dx Disabled (if FSx already low);

FSx Low to Dx Disabled (if BCLK8 low);

BCLK9 High to Dx Disabled (if FSx still high)

tDBT

Delay Time from BCLK and FSx Both High to TSx Low (Load = 100pF

plus 2 LSTTL loads)

tZBT

Delay Time from BCLK8 low to TSx Disabled (if FSx already low);

FSx Low to TSx Disabled

(if BCLK8 low);

BCLK9 High to TSx Disabled

(if FSx still high);

tDFD

Delay Time, FSx High to Data Valid (load = 100pF plus 2 LSTTL

loads, applies if FSx rises later than BCLK rising edge in non-

delayed data mode only)

tSDB

Setup Time, DR 0/1 Valid to BCLK Low

tHBD

Hold Time, BCLK Low to DR0/1 Invalid

Figure 5: Non Delayed Data Timing (short frame mode)

TS5070 - TS5071

19/32

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