MPC8313VRGDFB datasheet(96/100 Pages) FREESCALE

96 / 100 page

MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Document Revision History

3/2008

• In Table 63, added LBC_PM_REF_10 & LSRCID3 as muxed with USBDR_PCTL1

• In Table 63, added LSRCID2 as muxed with USBDR_PCTL0

• In Table 63, added LSRCID1 as muxed with USBDR_PWRFAULT

• In Table 63, added LSRCID0 as muxed with USBDR_DRIVE_VBUS

• In Table 63, moved T1, U2,& V2 from VDD to XCOREVDD.

• In Table 63, moved P2, R2, & T3 from VSS to XCOREVSS.

• In Table 63, moved P5, & U4 from VDD to XPADVDD.

• In Table 63, moved P3, & V4 from VSS to XPADVSS.

• In Table 63, removed “Double with pad” for AVDD1 and AVDD2 and moved AVDD1 and AVDD2 to Power

and Ground Supplies section

• In Table 63, added impedance control requirements for SD_IMP_CAL_TX (100 ohms to GND) and

SD_IMP_CAL_RX (200 ohms to GND).

• In Table 63, updated muxing in pinout to show new options for selecting IEEE 1588 functionality.

Added footnote 8

• In Table 63, updated muxing in pinout to show new LBC ECC boot enable control muxed with

eTSEC1_MDC

• Added pin type information for power supplies.

• Removed N1 and N3 from Vss section of Table 63. Added Therm0 and Therm1 (N1 and N3,

respectively). Added note 7 to state: “Internal thermally sensitive resistor, resistor value varies

linearly with temperature. Useful for determining the junction temperature.”

• In Table 65 corrected maximum frequency of Local Bus Frequency from “33–66” to 66 MHz

• In Table 65 corrected maximum frequency of PCI from “24–66” to 66 MHz

• Added “which is determined by RCWLR[COREPLL],” to the note in Section 20.2, “Core PLL

Configuration” about the VCO divider.

• Added “(VCOD)” next to VCO divider column in Table 68. Added footnote stating that core_clk

frequency must not exceed its maximum, so 2.5:1 and 3:1

core_clk:csb_clk ratios are invalid for

certain

csb_clk values.

• In Table 69, notes were confusing. Added note 3 for VCO column, note 4 for CSB (

csb_clk) column,

note 5 for USB ref column, and note 6 to replace “Note 1”. Clarified note 4 to explain erratum

eTSEC40.

• In Table 69, updated note 6 to specify USB reference clock frequencies limited to 24 and 48 for rev.

2 silicon.

• Replaced Table 71 “Thermal Resistance for TEPBGAII with Heat Sink in Open Flow”.

• Removed last row of Table 19.

• Removed 200 MHz rows from Table 21 and Table 5.

• Changed VIH minimum spec from 2.0 to 2.1 for clock, PIC, JTAG, SPI, and reset pins in Table 9,

Table 47, Table 54, Table 59, and Table 61.

• Added Figure 4 showing the DDR input timing diagram.

• In Table 19, removed “MDM” from the “MDQS-MDQ/MECC/MDM” text under the Parameter

column for the tCISKEW parameter. MDM is an output signal and should be removed from

the input AC timing spec table (tCISKEW).

• Added “and power” to rows 2 and 3 in Table 10

• Added the sentence “Once both the power supplies...” and PORESET to Section 2.2, “Power

Sequencing,” and Figure 3.

• In Figure 35, corrected “USB0_CLK/USB1_CLK/DR_CLK” with “USBDR_CLK”

• In Table 42, clarified that AC specs are for ULPI only.

6/2007

Initial release.

Table 73. Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

MPC8313VRGDFB 数据表(PDF) 96 Page - Freescale Semiconductor, Inc

MPC8313VRGDFB 数据表(HTML) 96 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载