MPC8313ECVRGDDB datasheet(33/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

8.4

eTSEC IEEE 1588 AC Specifications

Figure 19 provides the data and command output timing diagram.

Figure 19. eTSEC IEEE 1588 Output AC Timing

Figure 20 provides the data and command input timing diagram.

Figure 20. eTSEC IEEE 1588 Input AC Timing

The IEEE 1588 AC timing specifications are in Table 36.

Table 36. eTSEC IEEE 1588 AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5%.

Parameter/Condition

Symbol

Min

Typ

Max

Unit

Notes

TSEC_1588_CLK clock period

tT1588CLK

3.8

—

TRX_CLK × 9ns

1, 3

TSEC_1588_CLK duty cycle

tT1588CLKH/tT1588CLK

TSEC_1588_CLK peak-to-peak

jitter

tT1588CLKINJ

——

250

Rise time eTSEC_1588_CLK

(20%–80%)

tT1588CLKINR

1.0

—

2.0

Fall time eTSEC_1588_CLK

(80%–20%)

tT1588CLKINF

1.0

—

2.0

TSEC_1588_CLK_OUT clock

period

tT1588CLKOUT

× tT1588CLK

——

TSEC_1588_CLK_OUT duty cycle

tT1588CLKOTH

/tT1588CLKOUT

TSEC_1588_PULSE_OUT

tT1588OV

0.5

—

3.0

TSEC_1588_CLK_OUT

TSEC_1588_PULSE_OUT

TSEC_1588_TRIG_OUT

tT1588OV

tT1588CLKOUT

tT1588CLKOUTH

Note: The output delay is count starting rising edge if tT1588CLKOUT is non-inverting. Otherwise, it is

count starting falling edge.

TSEC_1588_CLK

TSEC_1588_TRIG_IN

tT1588TRIGH

tT1588CLK

tT1588CLKH

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