MPC8313ECVRGDDB datasheet(42/100 Pages) FREESCALE

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MPC8313E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 2.1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 28. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)

Figure 29 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

the MPC8313E SerDes reference clock input’s DC requirement, AC coupling has to be used. Figure 29

assumes that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC coupling. Its value could be ranged from 140 to 240

Ω depending on the clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8313E

SerDes3 reference clock’s differential input amplitude requirement (between 200 and 800 mV differential

peak). For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference

clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25

Ω.

Consult with the clock driver chip manufacturer to verify whether this connection scheme is compatible

with a particular clock driver chip.

Figure 29. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

n_REF_CLK

Clock Driver

100

Ω Differential PWB Trace

CLK_Out

LVDS CLK Driver Chip

10 nF

MPC8313E

SerDes Refer.

CLK Receiver

Clock Driver

n_REF_CLK

Clock Driver

100

Ω Differential PWB Trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK Driver Chip

MPC8313E

10 nF

CLK_Out

Clock Driver

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