PCA2000_2001_5

© NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 05 — 11 November 2008

8 of 28

NXP Semiconductors

PCA2000; PCA2001

32 kHz watch circuit with programmable adaptive motor pulse

7.5 Programming possibilities

The programming data is stored in OTP cells (EPROM cells). At delivery, all memory cells

are in state 0. The cells can be programmed to the state 1, but then there is no more set

back to state 0.

The programming data is organized in an array of four 8-bit words: word A contains the

time calibration, words B and C contain the setting for the monitor pulses and word D

contains the type recognition (see Table 4).

Table 4.

Words and bits

Word

Bit

1

2

3

4

5

6

7

8

A

number of 8192 Hz pulses to be removed

calibration

period

B

lowest stage: duty

cycle

number of driving

stages

highest stage:

duty cycle and

stretching

factory test bits

C

pulse width

maximum time delay between

positive and negative

detection pulses

EOL

voltage

factory test

bit

D

type

factory test bits

Table 5.

Description of word A bits

Bit

Value

Description

Inhibition time

1 to 7

-

adjust the number of the 8192 Hz pulses to be removed;

bit 1 is the MSB and bit 7 is the LSB

Calibration period

8

0

1 minute

1

2 minutes

Table 6.

Description of word B bits

Bit

Value

Description

Duty cycle lowest driving stage

1 to 2

00

37.5 %

01

43.75 %

10

50 %

11

56.25 %

Number of driving stages

3 to 4

00

3

01

4

10

5

11

6[1]

Duty cycle highest driving stage

5

0

75 %[2]

1

100 %