CS2000-CP

16

DS761PP1

5.2.3

Adjusting the Minimum Loop Bandwidth for CLK_IN

The CS2000 allows the minimum loop bandwidth of the Digital PLL to be adjusted between 1 Hz and 128

Hz using the ClkIn_BW[2:0] bits. The minimum loop bandwidth of the Digital PLL directly affects the jitter

transfer function; specifically, jitter frequencies below the loop bandwidth corner are passed from the PLL

input directly to the PLL output without attenuation. In some applications it is desirable to have a very low

minimum loop bandwidth to reject very low jitter frequencies, commonly referred to as wander. In others

it may be preferable to remove only higher frequency jitter, allowing the input wander to pass through the

PLL without attenuation.

Typically, applications in which the PLL_OUT signal creates a new clock domain from which all other sys-

tem clocks and associated data are derived will benefit from the maximum jitter and wander rejection of

the lowest PLL bandwidth setting. See Figure 12.

Systems in which some clocks and data are derived from the PLL_OUT signal while other clocks and data

are derived from the CLK_IN signal will often require phase alignment of all the clocks and data in the

system. See Figure 13. If there is substantial wander on the CLK_IN signal in these applications, it may

be necessary to increase the minimum loop bandwidth allowing this wander to pass through to the

CLK_OUT signal in order to maintain phase alignment. For these applications, it is advised to experiment

with the loop bandwidth settings and choose the lowest bandwidth setting that does not produce system

timing errors due to wandering between the clocks and data synchronous to the CLK_IN domain and

those synchronous to the PLL_OUT domain.

It should be noted that manual adjustment of the minimum loop bandwidth is not necessary to acquire

lock; this adjustment is made automatically by the Digital PLL. While acquiring lock, the digital loop band-

width is automatically set to a large value. Once lock is achieved, the digital loop bandwidth will settle to

the minimum value selected by the ClkIn_BW[2:0] bits.

Referenced Control

Register Location

ClkIn_BW[2:0] ....................... “Clock Input Bandwidth (ClkIn_BW[2:0])” on page 32

Figure 12. Low bandwidth and new clock domain

LRCK

SCLK

SDATA

MCLK

MCLK

Wander > 1 Hz

Wander and Jitter > 1 Hz Rejected

D0

D1

LRCK

SCLK

SDATA

Subclocks generated

from new clock domain.

or

PLL

BW = 1 Hz

CLK_IN

PLL_OUT

D0

D1

Jitter

Figure 13. High bandwidth with CLK_IN domain re-use

D0

D1

LRCK

SCLK

SDATA

MCLK

MCLK

Wander < 128 Hz

Jitter > 128 Hz Rejected

Wander < 128 Hz Passed to Output

LRCK

SCLK

SDATA

or

PLL

BW = 128 Hz

CLK_IN

PLL_OUT

Subclocks and data re-used

from previous clock domain.

Jitter

D0

D1