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CS2000-CP 数据表(PDF) 19 Page - Cirrus Logic

部件名 CS2000-CP
功能描述  Fractional-N Clock Synthesizer & Clock Multiplier
PDF  36 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS2000-CP 数据表(HTML) 19 Page - Cirrus Logic

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CS2000-CP
DS761PP1
19
set to 10), the Frequency Range Indicator would then reflect the frequency range of the audio sample rate.
An RUD of 512 would then generate the audio oversampling clocks as shown in Table 4.
5.3.5
Effective Ratio (REFF)
The Effective Ratio (REFF) is an internal calculation comprised of RUD and the appropriate modifiers, as
previously described. REFF is calculated as follows:
Frequency Synthesizer (Static Ratio) Mode: REFF = RUD
R
MOD
Hybrid PLL (Dynamic Ratio) Mode: REFF = RUD
R
MOD
Auto R-Mod
To simplify operation the device handles some of the ratio calculation functions automatically (such as
when the internal timing reference clock divider is set). For this reason, the Effective Ratio does not need
to be altered to account for internal dividers.
Ratio modifiers which would produce an overflow or truncation of REFF should not be used; For example
if RUD is 1024 an RMOD of 8 would produce an REFF value of 8192 which exceeds the 4096 limit of the
12.20 format. In all cases, the maximum and minimum allowable values for REFF are dictated by the fre-
quency limits for both the input and output clocks as shown in the “AC Electrical Characteristics” on
page 8.
Selection of the user defined ratio from the four stored ratios is made by using the RSel[1:0] bits unless
auto clock switching is enabled in which case the LockClk[1:0] bits also select the ratio (see “Manual Frac-
tional-N Source Selection for the Frequency Synthesizer” on page 20).
FsDetect[1:0]
Inferred Audio Sample Rate
when SysClk=12.288 MHz
Speed Mode (used for
audio converters)
Audio Oversampling
Clock
00
< 54.8 kHz
Single Speed
512 x
01
54.8 kHz to 128 kHz
Double Speed
256 x
10
> 128 kHz
Quad Speed
128 x
Table 4. Example Audio Oversampling Clock Generation from CLK_IN
Referenced Control
Register Location
Ratio0-3.................................“Ratio 0 - 3 (Address 06h - 15h)” on page 30
RModSel[2:0] ........................ “R-Mod Selection (RModSel[2:0])” section on page 28
AutoRMod .............................“Auto R-Modifier Enable (AutoRMod)” on page 29
Referenced Control
Register Location
RSel[1:0] ...............................“Ratio Selection (RSel[1:0])” on page 28
LockClk[1:0] .......................... “Lock Clock Ratio (LockClk[1:0])” section on page 29



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