DS626F3

9

CS5366

2. TYPICAL CONNECTION DIAGRAM

Figure 2. Typical Connection Diagram

For analog buffer configurations, refer to Cirrus Application Note AN241. Also, a low-cost single-ended-to-differen-

tial solution is provided on the Customer Evaluation Board.

FILT+

D

+

VA

V

+5V

5.1 Ω

1 μF

+

SDOUT2

DIF0/AD0/CS

Power Down

and Mode

Settings

0.01 μF

MODE0/SDA/CDOUT

MODE1/SCL/CCLK

REF_GND

VLC

μF

AIN

+

1

AIN

-

1

Channel 1 Analog

Input Buffer

AIN

+

2

AIN

-

2

Channel 2 Analog

Input Buffer

AIN

+

3

AIN

-

3

Channel 3 Analog

Input Buffer

AIN

+

4

AIN

-

4

Channel 4 Analog

Input Buffer

AIN

+

5

AIN

-

5

Channel 5 Analog

Input Buffer

AIN

+

6

AIN

-

6

Channel 6 Analog

Input Buffer

0.1

μF

VQ

GND

220 μ F

0.1

μF

+

1 μF

GND

DIF1/AD1/CDIN

RST

OVFL

0.01

0.01

μF

+5V to 3.3V

1 μF

+

A/D CONVERTER

CS5366

SDOUT1/TDM

SDOUT3/TDM

SCLK

MCLK

Timing Logic

and Clock

Audio Data

Processor

MDIV

CLKMODE

RESERVED

4,9

39

36

37

38

41

42

34

30

27

31

26

24

25

23

LRCK/FS

+5V to 1.8V

33

6

5

7

8

47

48

1

2

13

14

11

12

45

46

43

44

3, 8, 10, 15, 16,

17, 18, 19, 29, 32

35

40

VLS

μF

0.01

+5V to 1.8V

28

XTI

XTO

21

22

+5V

VX

20

Resistor may only be used if

VD is derived from VA. If used,

do not drive any other logic

from VD.