DS626F3

21

CS5366

4.4

Master and Slave Operation

CS5366 operation depends on two clocks that are synchronously derived from MCLK: SCLK and LRCK/FS.

See Section 4.5 on page 22 for a detailed description of SCLK and LRCK/FS.

The CS5366 can operate as either clock master or clock slave with respect to SCLK and LRCK/FS. In Mas-

ter Mode, the CS5366 derives SCLK and LRCK/FS synchronously from MCLK and outputs the derived

clocks on the SCLK pin (pin 25) and the LRCK/FS pin (pin 24), respectively. In Slave Mode, the SCLK and

LRCK/FS are inputs, and the input signals must be synchronously derived from MCLK by a separate device

such as another CS5366 or a microcontroller. Figure 8 illustrates the clock flow of SCLK and LRCK/FS in

both Master and Slave Modes.

The Master/Slave operation is controlled through the settings of M1 and M0 pins in Stand-Alone Mode or

by the M[1] and M[0] bits in the Global Mode Control Register in Control Port Mode. See Section 4.6 on page

23 for more information regarding the configuration of M1 and M0 pins or M[1] and M[0] bits.

Figure 8. Master/Slave Clock Flow

4.4.1

Synchronization of Multiple Devices

To ensure synchronous sampling in applications where multiple ADCs are used, the MCLK and LRCK must

be the same for all CS5366 devices in the system. If only one master clock source is needed, one solution

is to place one CS5366 in Master Mode, and slave all of the other devices to the one master, as illustrated

in Figure 9. If multiple master clock sources are needed, one solution is to supply all clocks from the same

external source and time the CS5366 reset de-assertion with the falling edge of MCLK. This will ensure that

all converters begin sampling on the same clock edge.

Figure 9. Master and Slave Clocking for a Multi-Channel Application

ADC as

clock

master

Controller

LRCK/FS

SCLK

ADC as

clock

slave

Controller

LRCK/FS

SCLK

Master

ADC

Slave1

ADC

Slave2

ADC

Slave3

ADC

SCLK & LRCK/FS