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AT89C5131A-RDTIL 数据表(PDF) 145 Page - ATMEL Corporation |
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AT89C5131A-RDTIL 数据表(HTML) 145 Page - ATMEL Corporation |
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145 / 186 page  145 AT89C5131A-L 4338F–USB–08/07 Table 103. UEPINT Register UEPINT (S:F8h read-only) USB Endpoint Interrupt Register Reset Value = 00h 7 6 5 4 3 2 1 0 - EP6INT EP5INT EP4INT EP3INT EP2INT EP1INT EP0INT Bit Number Bit Mnemonic Description 7 - Reserved The value read from this bit is always 0. Do not set this bit. 6 EP6INT Endpoint 6 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 6. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP6IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 5 EP5INT Endpoint 5 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 5. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP5IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 4 EP4INT Endpoint 4 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 4. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP4IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 3 EP3INT Endpoint 3 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 3. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP3IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 2 EP2INT Endpoint 2 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 2. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP2IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 1 EP1INT Endpoint 1 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 1. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP1IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared 0 EP0INT Endpoint 0 Interrupt This bit is set by hardware when an endpoint interrupt source has been detected on the endpoint 0. The endpoint interrupt sources are in the UEPSTAX register and can be: TXCMP, RXOUTB0, RXOUTB1, RXSETUP or STLCRC. A USB interrupt is triggered when the EP0IE bit in the UEPIEN register is set. This bit is cleared by hardware when all the endpoint interrupt sources are cleared |
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