AT89C5131A-RDTIL datasheet(37/186 Pages) ATMEL

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AT89C5131A-L

4338F–USB–08/07

Flash Registers and

Memory Map

The AT89C5131A-L Flash memory uses several registers:

•

Hardware register can be accessed with a parallel programmer.Some bits of the

hardware register can be changed, also, by API (i.e. X2 and BLJB bits of Hardware

security Byte) or ISP.

•

Software registers are in a special page of the Flash memory which can be

accessed through the API or with the parallel programming modes. This page,

called “Extra Flash Memory”, is not in the internal Flash program memory

addressing space.

Hardware Registers

The only hardware register of the AT89C5131A-L is called Hardware Security Byte

(HSB).

Bootloader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

•

When this bit is set the boot address is 0000h.

•

When this bit is reset the boot address is F400h. By default, this bit is cleared and

the ISP is enabled.

Flash Memory Lock Bits

The three lock bits provide different levels of protection for the on-chip code and data,

when programmed as shown in Table 38.

Table 37. Hardware Security Byte (HSB)

BLJB

OSCON1

OSCON0

LB2

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

X2 Mode

Cleared to force X2 mode (6 clocks per instruction)

Set to force X1 mode, Standard Mode (Default).

BLJB

Bootloader Jump Bit

Set this bit to start the user’s application on next reset at address 0000h.

Cleared this bit to start the bootloader at address F400h (default).

5-4

OSCON1-0

Oscillator Control Bits

These two bits are used to control the oscillator in order to reduce consumption.

OSCON1 OSCON0 Description

1 The oscillator is configured to run from 0 to 32 MHz

0 The oscillator is configured to run from 0 to 16 MHz

1 The oscillator is configured to run from 0 to 8 MHz

0 This configuration shouldn’t be set

Reserved

2-0

LB2-0

User Memory Lock Bits

See Table 38

AT89C5131A-RDTIL 数据表(PDF) 37 Page - ATMEL Corporation

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