CMS4A16LAH datasheet(39/46 Pages) FIDELIX

39 / 46 page

Rev. 0.4, Nov. ‘06

CMS4A16LAx–75xx

Concurrent Auto Precharge

If an access command with Auto Precharge is being executed ;

an access command (either a Read or Write ) is not allowed by

SDRAM’s. If this feature is allowed then the SDRAM supports

C o nc urre n t A u t o Pr ec h a r g e. Fid e lix SDRAMs

support Concurrent Auto Precharge.

Four cases where Concurrent Auto Precharge occurs are de-

fined below.

Read With Auto Precharge

1. Interrupted by a Read(with or without auto precharge): A

read to bank m will interrupt a Read on bank n, CAS latency

later. The precharge to bank n will begin when the Read to

bank m is registered. (Figure 25. )

2. Interrupted by a Write(with or without auto precharge): A

Write to bank m will interrupt a Read on bank n when registered.

DQM should be used two clocks prior to the Write command to

prevent bus contention. The Precharge to bank n will begin

when the write to bank m is registered. (Figure 26. )

Write with Auto Precharge

3. Interrupted by a Read(with or without auto precharge): A

Read to bank m will interrupt a Write on bank n when regis-

tered , with the data-out appearing CAS latency later. The Pre-

charge to bank n will begin after tWR is met, where tWR begins

when the Read to bank m is registered. The last valid Write to

bank n will be data-in registered one clock prior to the Read to

bank m.(Figure 27. )

4. Interrupted by a Write ( with or without auto Precharge): A

Write to bank m will interrupt a Write on bank n when registered.

The Precharge to bank n will begin after tWR is met ,where tWR

begins when the Write to bank m is registered. The latest valid

data Write to bank n will be data registered one clock prior to a

Write to bank m.( Figure 28. )

Figure 24. Clock Suspend During Read Burst - Burst of 4 (CAS latency =2)

CLK

Command

Address

Read

NOP

CKE

NOP

Internal

CLK

Bank

Col n

Dout

n+1

Dout

n+2

NOP

Dout

n+3

Dout

NOP

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