CMS4A16LAH datasheet(16/46 Pages) FIDELIX

16 / 46 page

Rev. 0.4, Nov. ‘06

CMS4A16LAx–75xx

Table 8. IDD Specifications and Conditions [21.22.26.27.].

Note :

21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C = TA = +85°C for IT parts) is ensured.

22. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be

powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh

requirement is exceeded.

23. All states and sequences not shown are illegal or reserved.

24. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

25. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.

26. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced

at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.

27. IDD specifications are tested after the device is properly initialized.

28. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.

29. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.

30. Input signals are changed one time during 20ns.

31. Unless otherwise note, input swing level is CMOS(V

IH/VIL=VDDQ/VSSQ).

32. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value

TA=25℃, f=1Mhz, VDD(typ)

Test Conditions

Units

CIN

Max

Output Capacitance

COUT

Input Capacitance

Description

Parameter

Capacitance[]

㎃

Operating Current: Burst Mode: Continuous Burst ; Read or Write : All banks

Active, CAS Latency =3[28.29.30.] , tCK=10ns

㎃

130

Auto Refresh Current : tRC ≥ tRC(min), tCK=10ns

IDD5

㎂

450

Self Refresh Current : CKE

≤ 0.2V, 4 Banks, tCK= ∞

IDD6

㎂

350

Self Refresh Current : CKE

≤ 0.2V, 2 Banks , tCK= ∞

㎂

300

Self Refresh Current : CKE

≤ 0.2V, 1 Banks, tCK= ∞

㎂

Deep power down, tCK= ∞

IDD7

IDD4

㎃

Precharge Standby Current in non power down mode : CKE

≥ V

IH(min),

/CS

≥ V

IH(min)

[28.29.30,31.]

, tCK=10ns

IDD2N

㎃

Active Standby Current in power down mode; CKE

≤ V

IL(max)

[28.29,30.31.]

, tCK=10ns

IDD3P

㎃

Active Standby Current in non power down mode (One Bank Active);

CKE

≥ V

IH(min), /CS ≥ VIH(min)

[28.29,30.31.]

, tCK=10ns

IDD3N

㎃

Units

IDD1

-75

0.4

Precharge Standby Current in power down mode : CKE

≤ V

IL(max) , tCK=10ns

IDD2P

Operating Current: Active Mode; Burst =2 ; Read or Write ; tRC ≥ tRC(min);

CAS Latency =3 [28.29.30.] , tCK=10ns

Description

Parameter

AC Test Loads

OUTPUT

Z0=50

30pF

VDDQ/2

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