Micrel

MICRF219

January 2009

2

M9999-011509

(408) 944-0800

Pin Configuration

1

RO1

GNDRF

ANT

GNDRF

Vdd

SQ

SHDN

16 RO2

SCLK

RSSI

CAGC

CTH

SEL1

DO

GND

15

14

13

12

11

10

9

2

3

4

5

6

8

SEL0 7

MICRF219AYQS

Pin Descr

-Pi

SOP

i

am

iption

16

n

P

Q

N

n

Pin Function

e

1

O

t: Reference resonator input connection to pierce oscillator stage. May also be

capacitance of

R 1

Reference Oscillator Inpu

driven by external reference signal of 200mVp-p to 1.5V p-p amplitude maximum. Internal

7pF to GND during normal operation.

2

ND

G

RF

Negative supply connection associated with ANT RF input.

3

AN

ed a matching network

T

Antenna Input: RF signal input from antenna. Internally AC coupled. It is recommend

with an inductor-to-RF ground be used to improve ESD protection.

4

GNDRF

Ground connection for ANT RF input.

5

D

ated as close to the VDD pin

V D

Positive supply connection for all chip functions. Bypass with 0.1uF capacitor loc

as possible.

6

S

p pulls the logic-input HIGH when the device is enabled.

applied the SQ pin. See

Q

Squelch Control Logic-Level Input. An internal pull-u

Bit D17 sets whether squelch is enabled or disabled when a logic-level signal is

Squelch Enable Truth-Table on page

7

E

l) when not in shutdown

serial interface contains

e.

S L0

Demodulator Filter Bandwidth Select Logic-Level Input:) Internal pull-up (3uA typica

or SLEEP mode. Used in conjunction with SEL1 to control D3 bandwidth LSB when

default setting. It does not need to be defined in SLEEP mod

8

H

-level HIGH places the

.

S DN

Shutdown control Logic-Level Input. A logic-level LOW enables the device. A logic

device in low-power shutdown mode. An internal pull-up pulls the logic input HIGH

9

N

G D

Negative supply connection for all chip functions except for RF input.

10

D

king test is acceptable. A

output during normal operation this pin is also used as a CMOS Schmitt input for serial

modes.

O

Data Input and Output. Demodulated data output. May be blanked until bit chec

current limited CMOS

interface data. A 25kΩ pull-down is present when device is in shutdown and sleep

11

E

ical) pull-up when not in shutdown or

B, when serial interface contains

default setting. It does not need to be defined in SLEEP mode.

S L1

Demodulator Filter Bandwidth Select Logic-Level Input: Internal (3uA typ

SLEEP mode. Used in conjunction with SEL0, to control D4 bandwidth MS

12

CTH

Demodulation threshold voltage integration capacitor. Capacitor-to-GND sets the settling time for the

demodulation data slicing level. Values above 1nF are recommended and should be optimized for data rate

and data profile.

13

CAGC

AGC filter capacitor. A capacitor, normally greater than 0.47μF, is connected from this pin-to-GND

14

RSSI

Received signal strength indication (output): Output is from a switched capacitor integrating op amp with

220Ω typical output impedance.

15

SCLK

Serial interface input clock. CMOS Schmitt input. A 25kΩ pull-down is present when device is in shutdown

mode.

16

RO2

Reference resonator connection. Internal capacitance of 7pF to GND during normal operation.