TMS320VC33 datasheet(13/57 Pages) TI

13 / 57 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E − FEBRUARY 1999 − REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

PLL and clock oscillator control (continued)

Typical crystals in the 8−30 MHz range have a series resistance of 25

Ω, which increases below 8 MHz. To

maintain proper filtering and phase relationships, Rd and Zout of the oscillator circuit should be 10x−40x that of

the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower

frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output

impedance, C1 load capacitor, and Rd (if present). The crystal and C2 input load capacitor then refilters this

signal, resulting in a XIN signal that is 75−85% of the oscillator supply voltage.

NOTE: Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2

internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals.

NOTE: Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5.

A similar filter can be used to isolate the PLLVSS, as shown in Figure 6. PLLVDD can also be directly connected

to CVDD.

Table 2. Typical Crystal Circuit Loading

FREQUENCY (MHz)

Rd (

Ω)

C1 (pF)

C2 (pF)

CL† (pF)

RL† (

Ω)

4.7k

200

2.2k

470

† CL and RL are typical internal series load capacitance and resistance of the crystal.

XOUT

XIN

Crystal

EXTCLK

PLLVSS

CVDD

100

Ω

PLLVDD

0.1

µF

0.01

µF

Figure 5. Self-Oscillation Mode

TMS320VC33 数据表(PDF) 13 Page - Texas Instruments

TMS320VC33 数据表(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

数据表下载