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TMS320VC549 数据表(PDF) 39 Page - Texas Instruments |
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TMS320VC549 数据表(HTML) 39 Page - Texas Instruments |
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39 / 60 page ![]() TMS320VC549 FIXEDPOINT DIGITAL SIGNAL PROCESSOR SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000 39 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 instruction acquisition (IAQ), interrupt acknowledge (IACK), external flag (XF), and TOUT timing switching characteristics over recommended operating conditions for IAQ and IACK [H = 0.5 tc(CO)] (see Figure 18) PARAMETER ’549-80 ’549-100 ’549-120 UNIT PARAMETER MIN MAX MIN MAX UNIT td(CLKL-IAQL) Delay time, IAQ low from CLKOUT low – 1 5 – 1 4 ns td(CLKL-IAQH) Delay time, IAQ high from CLKOUT low – 1 5 – 1 4 ns td(A)IAQ Delay time, address valid before IAQ low 4 4 ns td(CLKL-IACKL) Delay time, IACK low from CLKOUT low 0 5 0 4 ns td(CLKL-IACKH) Delay time , IACK high from CLKOUT low 0 5 0 4 ns td(A)IACK Delay time, address valid before IACK low 3 3 ns th(A)IAQ Hold time, address valid after IAQ high – 3 – 3 ns th(A)IACK Hold time, address valid after IACK high – 3 – 3 ns tw(IAQL) Pulse duration, IAQ low 2H–3 2H–3 ns tw(IACKL) Pulse duration, IACK low 2H–3 2H–3 ns MSTRB IACK IAQ A[15:0] CLKOUT td(A)IACK td(A)IAQ tw(IACKL) th(A)IACK td(CLKL-IACKL) tw(IAQL) th(A)IAQ td(CLKL-IAQL) td(CLKL-IACKH) td(CLKL-IAQH) Figure 18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timing |
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