TMS320VC549 datasheet(2/60 Pages) TI

2 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Table of Contents

Description

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pin Assignments

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal Descriptions

. . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings

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Recommended Operating Conditions

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Electrical Characteristics

. . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information

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Timing Parameter Symbology

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Signal Transition Reference Points

. . . . . . . . . . . . . .

Internal Oscillator With External Crystal

. . . . . . . . .

Divide-By-Two/Divide-By-Four Clock Option

. . . . .

Multiply-By-N Clock Option

. . . . . . . . . . . . . . . . . . . .

Memory and Parallel I/O Interface Timing

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Timing Requirements for a Parallel I/O Port Read

SPICE Simulation Results

. . . . . . . . . . . . . . . . . . . . .

Ready Timing for Externally Generated Wait States 31

HOLD and HOLDA Timing

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Reset, BIO, Interrupt, and MP/MC Timings

. . . . . . .

Serial Port Receive Timing

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Buffered Serial Port Receive Timing

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Serial-Port Receive Timing in TDM Mode

. . . . . . . .

Host-Port Interface Timing

. . . . . . . . . . . . . . . . . . . . .

Mechanical Data

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description

The TMS320VC549 fixed-point, digital signal processor (DSP) (hereafter referred to as the ’549) is based on

an advanced modified Harvard architecture that has one program memory bus and three data memory buses.

The processor also provides an arithmetic logic unit (ALU) that has a high degree of parallelism,

application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The ’549 also utilizes

a highly specialized instruction set, which is the basis of its operational flexibility and speed.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the

high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions

with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be

transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,

and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’549

includes the control mechanisms to manage interrupts, repeated operations, and function calls.

This data sheet contains the pin layouts, signal descriptions, and electrical specifications for the TMS320VC549

DSP. For additional information, see the

TMS320C54x, TMS320LC54x, TMS320VC54x Fixed-Point Digital

Signal Processors data sheet (literature number SPRS039). The SPRS039 is considered a family functional

overview and should be used in conjunction with this data sheet.

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