TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

30

POST OFFICE BOX 1443

ready timing for externally generated wait states

Figure 12, and Figure 13)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

tsu(RDY)

Setup time, READY before CLKOUT low

6

5

5

ns

th(RDY)

Hold time, READY after CLKOUT low

0

0

0

ns

tv(RDY)MSTRB

Valid time, READY after MSTRB low‡

4H–10

4H–8

4H–8

ns

th(RDY)MSTRB

Hold time, READY after MSTRB low‡

4H

4H

4H

ns

tv(RDY)IOSTRB

Valid time, READY after IOSTRB low‡

5H–10

5H–8

5H–8

ns

th(RDY)IOSTRB

Hold time, READY after IOSTRB low‡

5H

5H

5H

ns

tv(MSCL)

Valid time, MSC low after CLKOUT low

0

5

0

4

0

4

ns

tv(MSCH)

Valid time, MSC high after CLKOUT low

0

5

0

4

0

4

ns

† The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by

READY, at least two software wait states must be programmed. READY is not sampled until the completion of the internal software wait states.

‡ These timings are included for reference only. The critical timings for READY are those referenced to CLKOUT.