TMS320VC549 datasheet(20/60 Pages) TI

20 / 60 page

TMS320VC549

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS078F – SEPTEMBER 1998 – REVISED MAY 2000

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

memory and parallel I/O interface timing (continued)

timing requirements for a memory read (MSTRB = 0) [H = 0.5 tc(CO)]†‡ (see Figure 5)

’549-80

’549-100

’549-120

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

ta(A)M

Access time, read data access from address valid

2H–9

2H–8

ta(MSTRBL)

Access time, read data access from MSTRB low

2H–8

2H–7

tsu(D)R

Setup time, read data before CLKOUT low

th(D)R

Hold time, read data after CLKOUT low

th(A-D)R

Hold time, read data after address invalid

th(D)MSTRBH Hold time, read data after MSTRB high

† Address, PS, and DS timings are all included in timings referenced as address.

‡ See Table 1, Table 2, and Table 3 for address bus timing variation with load capacitance.

TMS320VC549 数据表(PDF) 20 Page - Texas Instruments

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