TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

15

POST OFFICE BOX 655303

TNETE2004 registers

The TNETE2004 incorporates management-data interface to allow register-based management operations for

each PHY module. Normal operation of the TNETE2004 is possible without use of management-data interface

since all the essential signals for operation are accessible through the device pins; however, some additional

features are accessible only through the management-data interface. If management-data interface is not being

used, DEVSEL, MDCLK, and MDIO all can be tied low.

Some features are controllable by both pins and registers. A feature is controlled by the pin until a write operation

is performed on the register controlling the feature. From then until the device is reset, the value on the pin is

ignored.

The TNETE2004 registers are accessible through the Mll-management interface. The IEEE Std 802.3 Mll serial

protocol allows for up to 32 different PHYs, with up to 32 (16-bit-wide) internal registers in each device.

The TNETE2004 implements 11 registers (three of which are hardwired) on each PHY and three additional

overview registers that allow software drivers to access all four PHYs in a single operation. User programming

of the SNI is implemented through the pin-polarity register. These all-PHY registers are mapped into the

addressing space on PHY0.

Figure 3 shows the TNETE2004 device register map. The registers, shown shaded, are the generic registers

mandated by the Mll specification. The unshaded registers are TI-specific registers.

PHY Generic Control Register (see Figure 6, Table 3)

GEN_sts

QuadPHY_sts

QuadPHY_4ctl

QuadPHY_4sts

QuadPHY_4ctl2

QuadPHY_ppol

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x08 to 0x0f

0x10

0x11

0x12

0x13

0x14

0x15

0x16

Address

PHY Generic Status Register (see Figure 7, Table 4)

PHY Generic Identifier (high), hardwired 0x4000

PHY Generic Identifier (low), hardwired 0x5051

Auto-Negotiation Advertisement (see Figure 8, Table 5)

Auto-Negotiation Link-Partner Ability (see Figure 9, Table 6)

Auto-Negotiation Expansion (see Figure 10, Table 7)

Auto-Negotiation Next-Page Transmit (see Figure 11)

Reserved by IEEE Std 802.3

TNETE2004 Identification, Hardwired

TNETE2004 Control Register (see Figure 12, Table 8)

TNETE2004 Status Register (see Figure 13, Table 9)

TNETE2004 Nibble-Based Control Register, Overview (see Figure 14, Table 10)

TNETE2004 Nibble-Based Status Register, Overview (see Figure 15, Table 11)

TNETE2004 Nibble-Based Control Register 2, Overview (see Figure 16, Table 12)

TNETE2004 Pin-Polarity Register (see Figure 17, Table 13)

Register

AN_NEXTPAGE

Reserved

GEN_id_hi

GEN_id_lo

AN_far_end_ability

AN_exp

AN_advertisement

GEN_ctl

QuadPHY_ID

QuadPHY_ctl

GEN_sts

Figure 3. TNETE2004 Registers

The default or IDLE state of the two-wire Mll is a logic 1. All 3-state drivers are disabled, and the TNETE2004

pullup resistor pulls the MDIO line to a logic 1. Before initiating any other transaction, the station management

entity sends a sequence of 32 contiguous logic 1 bits on MDIO and 32 corresponding contiguous logic 1 bits

on MDCLK. This sequence provides the TNETE2004 with a pattern that it can use to establish synchronization.

The TNETE2004 responds to no other transactions until it recognizes a sequence of 32 contiguous logic 1 bits

on MDIO with 32 contiguous logic 1 bits on MDCLK.

Frame format of the generic registers is in accordance with Mll specifications as shown in Figures 4 and 5.