TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

19

POST OFFICE BOX 655303

auto-negotiation advertisement register at 0x4

BYTE 1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BYTE 0

0

N

X

T

P

A

G

E

R

E

S

E

R

V

E

D

R

F

L

T

TECHNOLOGY ABILITY FIELD

SELECTOR FIELD

Figure 8. Auto-Negotiation Advertisement Register

Table 5. Auto-Negotiation Advertisement-Register Bit Functions

BIT

FUNCTION

DIRECTION†

DEFAULT

NO.

NAME

FUNCTION

DIRECTION†

DEFAULT

15

NXTPAGE

Auto-negotiation next page. NXTPAGE should be set when there is a next

page to transmit. The next page is set by writing to AN_NEXTPAGE.

RO

0

14

RESERVED

Reserved

RO

0

13

RFLT

Remote fault. RFLT enabled indicates to the link partner that there is a fault

condition on the TNETE2004. RFLT can be set only by a management entity.

This bit does not imply an internal test mode.

R/W

0

12–5

TECHNOLOGY

ABILITY FIELD‡

This field indicates the technology abilities advertised to the link partner.

Unsupported technologies cannot be transmitted, hence, only two bits have

significance.

Bit 6: Full-duplex 10BASE-T

Bit 5: Half-duplex 10BASE-T

All other bits are hardwired to 0.

R/W

Bits 5 and 6

are set to 1, all

others are set

to 0.

4–0

SELECTOR

FIELD

This field specifies the format of the page to be transmitted. This PHY supports

only standard IEEE Std 802.3u base pages, so this field is hardwired to 00001.

RO

† RO = read only, R/W = read/write

‡ After a reset, the PHY attempts to drive the duplex pin. If the pin can be driven high, then bit 6 is set. If the pin can be driven low, then bit 5 is

set.

auto-negotiation link-partner ability register at 0x5

This register contains the most recently received link control word from the remote PHY. Writing to this register

has no effect. The contents of this register are undefined unless either ACOMPLETE (bit 5, register 1) or

PAGERX (bit 1, register 6) are set.

When ACOMPLETE is set, the bits in this register are as described in Table 6.

BYTE 1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BYTE 0

0

L

P

N

X

T

P

A

G

E

R

E

S

E

R

V

E

D

L

P

R

F

L

T

LINK-PARTNER

TECHNOLOGY ABILITY FIELD

LINK-PARTNER

SELECTOR FIELD

Figure 9. Auto-Negotiation Link-Partner Ability Register