TNETE2004

MDIO-MANAGED QuadPHY

FOUR 10BASE-T PHYSICAL-LAYER INTERFACES

SPWS023D – OCTOBER 1996 – REVISED OCTOBER 1997

21

POST OFFICE BOX 655303

expansion register

Refer to Table 7 for the bit definition of the expansion register.

Table 7. Auto-Negotiation Expansion-Register Bit Functions

BIT

FUNCTION

DIRECTION†

NO.

NAME

FUNCTION

DIRECTION†

15–5

RESERVED

Reserved. Read as 0.

RO

4

PARDETFLT

Parallel detection fault. PARDETFLT indicates multiple links established. This is not supported

by this PHY; hence, PARDETFLT is always read as the inverse of LINK.

RO

3

LPNPABLE

Link-partner next-page able. LPNPABLE indicates that the link partner is next-page capable.

RO

2

NPABLE

Next-page able. This PHY is capable of exchanging next pages, so NPABLE is hardwired to 1.

RO

1

PAGERX

Page received. PAGERX is set after three identical and consecutive link code words have been

received from the link partner. PAGERX is cleared when the link-partner ability register is read.

RO

0

LPANABLE

Link-partner auto-negotiation able. LPANABLE is set to 1 when the PHY has received fast link

pulses from the link partner.

RO

† RO = read only

auto-negotiation next_page transmit register – AN_NEXTPAGE at 0x07

BYTE 1

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

BYTE 0

0

NEXTPAGE DATA

Figure 11. Auto-Negotiation Next_Page Transmit Register

When written to, this register sets the next page to be transmitted by way of auto-negotiation. Writing to this

register instructs the auto-negotiation system to transmit a next page.

TNETE2004 identification register, QUADB_ID at 0x10

This register is hardwired to the value 0x0005. Writing to this register has no effect.