数据搜索系统，热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

预览 PDF HTML

ADP8860ACPZ-R7 数据表(PDF) 30 Page - Analog Devices

部件名 ADP8860ACPZ-R7
功能描述  Charge Pump, 7-Channel Smart LED Driver with I2C Interface
PDF  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP8860ACPZ-R7 数据表(HTML) 30 Page - Analog Devices

Back Button ADP8860ACPZ-R7 Datasheet HTML 26Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 27Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 28Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 29Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 30Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 31Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 32Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 33Page - Analog Devices ADP8860ACPZ-R7 Datasheet HTML 34Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 30 / 52 page
background image
ADP8860
Rev. 0 | Page 30 of 52
Bit Name
Bit No.
Description
CMP_IEN
0
When the CMP_INT status bit is set after an enabled comparator trips, an interrupt is raised if the CMP_IEN flag is
enabled.
1 = the main comparator interrupt is enabled.
0 = the main comparator interrupt is disabled (the CMP_INT flag continues to assert).
BACKLIGHT REGISTER DESCRIPTIONS
Configuration Register (CFGR)—Register 0x04
Table 16. CFGR Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
SEL_AB
CMP2_SEL
BLV
Law
FOVR
Table 17. Bit Descriptions for the CFGR Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
SEL_AB
6
1 = selects the second phototransistor (CMP_IN2) to control the backlight.
0 = selects the main phototransistor (CMP_IN) to control the backlight.
CMP2_SEL
5
1 = the second phototransistor is enabled; the current sink on D6 is disabled.
0 = the second phototransistor is disabled.
BLV
4:3
Brightness level. This field indicates the brightness level at which the device is operating. The software may force the
backlight to operate at one of the three brightness levels. Setting CMP_AUTOEN high (Register 0x01) sets these
values automatically and overwrites any previously written values.
00 = Level 1 (daylight).
01 = Level 2 (office).
10 = Level 3 (dark).
11 = off (backlight set to 0 mA).
Law
2:1
Backlight transfer law.
00 = linear law DAC, linear time steps.
01 = square law DAC, linear time steps.
10 = square law DAC, nonlinear time steps (Cubic 10).
11 = square law DAC, nonlinear time steps (Cubic 11).
FOVR
0
Backlight fade override.
1 = the backlight fade override is enabled.
0 = the backlight fade override is disabled.
Backlight Sink Enable (BLSEN)—Register 0x05
Table 18. BLSEN Bit Map
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
D7EN
D6EN
D5EN
D4EN
D3EN
D2EN
D1EN
Table 19. Bit Descriptions for the BLSEN Register
Bit Name
Bit No.
Description
N/A
7
Reserved.
D7EN
6
Diode 7 backlight sink enable.
1 = selects LED7 as an independent sink.
0 = connects LED7 sink to backlight enable (BL_EN).
D6EN
5
Diode 6 backlight sink enable.
1 = selects LED6 as an independent sink.
0 = connects LED6 sink to backlight enable (BL_EN).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com